View MPC9774_480979.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order Number: MPC9774/D Rev 1, 04/2002
Product Preview
3.3V/2.5V 1:14 LVCMOS PLL Clock Generator
The MPC9774 is a 3.3V or 2.5V compatible, 1:14 PLL based clock generator targeted for high performance low-skew clock distribution in mid-range to high-performance networking, computing and telecom applications. With output frequencies up to 125 MHz and output skews less than 300 ps1 the device meets the needs of the most demanding clock applications. Features * 1:14 PLL based low-voltage clock generator
MPC9774
3.3V/2.5V 1:14 LVCMOS PLL CLOCK GENERATOR
* * * * * * * * * * *
2.5V or 3.3V power supply Internal power-on reset Generates clock signals up to 125 MHz Maximum output skew of 300 ps1 Two LVCMOS PLL reference clock inputs External PLL feedback supports zero-delay capability Various feedback and output dividers (see application section) Supports up to three individual generated output clock frequencies Drives up to 28 clock lines Ambient temperature range 0C to +85C Pin and function compatible to the MPC974
FA SUFFIX 52 LEAD LQFP PACKAGE CASE 848D
Functional Description The MPC9774 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the MPC9774 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path. The reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency range. The MPC9774 features frequency programmability between the three output banks outputs as well as the output to input relationships. Output frequency ratios of 1:1, 2:1, 3:1, 3:2 and 3:2:1 can be realized. Additionally, the device supports a separate configurable feedback output which allows for a wide variety of of input/output frequency multiplication alternatives. The VCO_SEL pin provides an extended PLL input reference frequency range. The REF_SEL pin selects the internal crystal oscillator or the LVCMOS compatible inputs as the reference clock signal. Two alternative LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL characteristics do not apply. The MPC9774 has an internal power-on reset. The MPC9774 is fully 2.5V and 3.3V compatible and requires no external loop filter components. All inputs (except XTAL) accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines. For series terminated transmission lines, each of the MPC9774 outputs can drive one or two traces giving the devices an effective fanout of 1:12. The device is pin and function compatible to the MPC974 and is packaged in a 52-lead LQFP package.
1. Final specification of this parameter is pending characterization.
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
(c) Motorola, Inc. 2002
1
MPC9774
All input resistors have a value of 25k VCC CCLK0 CCLK1 CCLK_SEL 0
Ref
Bank A
QA0 QA1
0
VCO
/2 /4
0 1
/2, /4 /2, /4 /4, /6 /4, /6, /8, /12
1
1
CLK STOP
QA2 QA3 QA4
PLL
200-500 MHz
VCC
Bank B
QB0 QB1
FB_IN PLL_EN VCO_SEL FSEL_A FSEL_B FSEL_C FSEL_FB[1:0]
FB
CLK STOP
QB2 QB3 QB4
2
Bank C CLK STOP
QC0 QC1 QC2 QC3
VCC CLK_STOP VCC MR/OE POWER-ON RESET
QFB
Figure 1. MPC9774 Logic Diagram
FB_IN GND GND GND
VCC
VCC
VCC
QFB
QB1
QB2
QB3
QB4
39 38 37 36 35 34 33 32 31 30 29 28 27 QB0 VCC NC GND QC3 VCC QC2 GND QC1 VCC QC0 GND VCO_SEL 40 41 42 43 44 45 46 47 48 49 50 51 52 1 2 3 4 5 6 7 8 9 10 11 12 13 26 25 24 23 22 21 VCC QA0 GND QA1 VCC QA2 FSEL_FB1 GND QA3 VCC QA4 GND FSEL_FB0
MPC9774
NC 20 19 18 17 16 15 14 VCC_PLL
CCLK_SEL
PLL_EN
CCLK0
MR/OE
FSEL_C
CCLK1
GND
FSEL_B
Figure 2. MPC9774 52-Lead Package Pinout (Top View)
MOTOROLA
CLK_STOP
2
FSEL_A
VCC
NC
TIMING SOLUTIONS
MPC9774
Table 1. PIN CONFIGURATION
Pin CCLK0 CCLK1 FB_IN CCLK_SEL VCO_SEL PLL_EN MR/OE CLK_STOP FSEL_A FSEL_B FSEL_C FSEL_FB[1:0] QA[4:0] QB[4:0] QC[3:0] QFB GND VCC_PLL VCC I/O Input Input Input Input Input Input Input Input Input Input Input Input Output Output Output Output Supply Supply Supply Type LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Ground VCC VCC PLL reference clock Alternative PLL reference clock PLL feedback signal input, connect to QFB LVCMOS clock reference select VCO operating frequency select PLL enable/PLL bypass mode select Output enable/disable (high-impedance tristate) and device reset Output enable/clock stop (logic low state) Frequency divider select for bank A outputs Frequency divider select for bank B outputs Frequency divider select for bank C outputs Frequency divider select for the QFB output Clock outputs (Bank A) Clock outputs (Bank B) Clock outputs (Bank C) PLL feedback output. Connect to FB_IN. Negative power supply PLL positive power supply (analog power supply). It is recommended to use an external RC filter for the analog power supply pin VCC_PLL. Please see applications section for details. Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation Function
Table 2. Function Table (MPC9774 configuration controls)
Control CCLK_SEL VCO_SEL PLL_EN Default 0 0 1 0 Selects CCLK0 as PLL refererence signal input Selects VCO / 2. The VCO frequency is scaled by a factor of 2 (high input frequency range) Test mode with the PLL bypassed. The reference clock is substituted for the internal VCO output. MPC9774 is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. QA, QB an QC outputs disabled in logic low state. QFB is not affected by CLK_STOP. CLK_STOP deassertion may cause the initial output clock pulse to be distorted. Outputs disabled (high-impedance state) and reset of the device. During reset/output disable the PLL feedback loop is open and the internal VCO is tied to its lowest frequency. The MPC9774 requires reset after any loss of PLL lock. Loss of PLL lock may occur when the external feedback path is interrupted. The length of the reset pulse should be greater than one reference clock cycle (CCLKx). The device is reset by the internal power-on reset (POR) circuitry during power-up. 1 Selects CCKL1 as PLL reference signal input Selects VCO / 4. The VCO frequency is scaled by a factor of 4 (low input frequency range). Normal operation mode with PLL enabled.
CLK_STOP
1
Outputs enabled (active)
MR/OE
1
Outputs enabled (active)
VCO_SEL, FSEL_A, FSEL_B, FSEL_C and FSEL_FB[1:0] control the operating PLL frequency range and input/output frequency ratios. See Table 3 and Table 4 for the device frequency configuration.
TIMING SOLUTIONS
3
MOTOROLA
MPC9774
Table 3. Function Table (Output Dividers Bank A, B, and C)
VCO_SEL 0 0 1 1 FSEL_A 0 1 0 1 QA[4:0] VCO / 4 VCO / 8 VCO / 8 VCO / 16 VCO_SEL 0 0 1 1 FSEL_B 0 1 0 1 QB[4:0] VCO / 4 VCO / 8 VCO / 8 VCO / 16 VCO_SEL 0 0 1 1 FSEL_C 0 1 0 1 QC[3:0] VCO / 8 VCO / 12 VCO / 16 VCO / 24
Table 4. Function Table (QFB)
VCO_SEL 0 0 0 0 1 1 1 1 FSEL_B1 0 0 1 1 0 0 1 1 FSEL_B0 0 1 0 1 0 1 0 1 QFB VCO / 8 VCO / 16 VCO / 12 VCO / 24 VCO / 16 VCO / 32 VCO / 24 VCO / 48
MOTOROLA
4
TIMING SOLUTIONS
MPC9774
Table 5. General Specifications
Symbol VTT MM HBM LU CPD CIN Characteristics Output termination voltage ESD protection (Machine model) ESD protection (Human body model) Latch-up immunity Power dissipation capacitance Input capacitance 200 2000 200 12 4.0 Min Typ VCC / 2 Max Unit V V V mA pF pF Per output Inputs Condition
Table 6. Absolute Maximum Ratingsa
Symbol VCC VIN VOUT IIN IOUT a. Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Characteristics Min -0.3 -0.3 -0.3 Max 3.6 VCC + 0.3 VCC + 0.3 20 50 Unit V V V mA mA Condition5
TS Storage temperature -65 125 C Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied.
Table 7. DC Characteristics (VCC = 3.3V 5%, TA = 0C to +85C)
Symbol VCC_PLL VIH VIL VOH VOL ZOUT IIN ICC_PLL ICCQ a. b. Characteristics PLL supply voltage Input high voltage Input low voltage Output High Voltage Output Low Voltage Output impedance Input Currentb Maximum PLL Supply Current 14 - 17 200 3.0 5.0 2.4 0.55 0.30 Min 2.325 2.0 Typ Max VCC VCC + 0.3 0.8 Unit V V V V V V A mA VIN = VCC or GND VCC_PLL Pin Condition LVCMOS LVCMOS LVCMOS IOH = -24 mAa IOL = 24 mA IOL = 12 mA
Maximum Quiescent Supply Current 1.0 mA All VCC Pins The MPC9774 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines. Inputs have pull-down or pull-up resistors affecting the input current.
TIMING SOLUTIONS
5
MOTOROLA
MPC9774
Table 8. AC Characteristics (VCC = 3.3V 5%, TA = 0C to + 85C)a b
Symbol fref Characteristics Input reference frequency /8 feedback /12 feedback /16 feedback /24 feedback /32 feedback /48 feedback Min 25.0 16.6 12.5 8.33 6.25 4.16 Typ Max 62.5 41.6 31.25 20.83 15.625 10.41 TBD 200 /4 output /8 output /12 output /16 output /24 output 50.0 25.0 16.6 12.5 8.33 40 150 300 45 0.1 50 55 1.0 8 8 RMS (1 )f RMS (1 ) RMS (1 ) TBD TBD TBD 500 125.0 62.5 41.6 31.25 20.83 60 1.0 Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz % ns ps ps % ns ns ns ps ps ps kHz 0.55 to 2.4V 0.8 to 2.0V PLL locked PLL locked Condition PLL locked
Input reference frequency in PLL bypass modec fVCO fMAX VCO frequency ranged Output Frequency
PLL bypass
frefDC tr, tf t() tsk(O) DC tr, tf tPLZ, HZ tPZL, LZ tJIT(CC) tJIT(PER) tJIT() BW a b c d e f g
Reference Input Duty Cycle CCLKx Input Rise/Fall Time Propagation Delay (static phase offset) CCLKx or FB_IN Output-to-output Skewe Output duty cycle Output Rise/Fall Time Output Disable Time Output Enable Time Cycle-to-cycle jitter Period Jitter I/O Phase Jitter PLL closed loop bandwidthg
tLOCK Maximum PLL Lock Time 10 ms All AC characteristics are design targets and subject to change upon device characterization. AC characteristics apply for parallel output termination of 50 to VTT. In bypass mode, the MPC9774 divides the input reference clock. The input reference frequency must match the VCO lock range divided by the total feedback divider ratio: fref = fVCO / (M VCO_SEL). See application section for part-to-part skew calculation. See application section for a jitter calculation for other confidence factors than 1 . -3 dB point of PLL transfer characteristics.
MOTOROLA
6
TIMING SOLUTIONS
MPC9774
Table 9. DC Characteristics (VCC = 2.5V 5%, TA = 0C to + 85C)
Symbol VCC_PLL VIH VIL VOH VOL ZOUT IIN ICC_PLL ICC a. Input high voltage Input low voltage Output High Voltage Output Low Voltage Output impedance Input Currentb Maximum PLL Supply Current Maximum Quiescent Supply Current 17 - 20 200 2.0 5.0 1.0 Characteristics PLL supply voltage Min 2.325 1.7 -0.3 1.8 0.6 Typ Max VCC VCC + 0.3 0.7 Unit V V V V V Condition LVCMOS LVCMOS LVCMOS IOH =-15 mAa IOL = 15 mA VIN = VCC or GND VCCA Pin All VCC Pins
W
A mA mA
b.
The MPC9774 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines per output. Inputs have pull-down or pull-up resistors affecting the input current.
Table 10. AC Characteristics (VCC = 2.5V 5%, TA = 0C to + 85C)a b
Symbol fref Characteristics Input reference frequency /8 feedback /12 feedback /16 feedback /24 feedback /32 feedback /48 feedback Min 25.0 16.6 12.5 8.33 6.25 4.16 Typ Max 50.0 33.3 25.0 16.6 12.5 8.3 TBD 200 /4 output /8 output /12 output /16 output /24 output 50.0 25.0 16.6 12.5 8.33 40 150 300 45 0.1 50 55 1.0 10 10 RMS (1 )f RMS (1 ) RMS (1 ) TBD TBD TBD TBD 400 100.0 50.0 33.3 25.0 16.6 60 1 Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz % ns ps ps % ns ns ns ps ps ps kHz 0.6 to 1.8V 0.7 to 1.7V PLL locked PLL locked Condition PLL locked
Input reference frequency in PLL bypass modec fVCO fMAX VCO frequency ranged Output Frequency
PLL bypass
frefDC tr, tf t() tsk(O) DC tr, tf tPLZ, HZ tPZL, LZ tJIT(CC) tJIT(PER) tJIT() BW a. b. c. d. e. f. g.
Reference Input Duty Cycle CCLKx Input Rise/Fall Time Propagation Delay (static phase offset) CCLKx or PCLK to FB_IN Output-to-output Skewe Output duty cycle Output Rise/Fall Time Output Disable Time Output Enable Time Cycle-to-cycle jitter Period Jitter I/O Phase Jitter PLL closed loop bandwidthg
tLOCK Maximum PLL Lock Time 10 ms All AC characteristics are design targets and subject to change upon device characterization. AC characteristics apply for parallel output termination of 50 to VTT. In bypass mode, the MPC9774 divides the input reference clock. The input reference frequency must match the VCO lock range divided by the total feedback divider ratio: fref = fVCO / (M VCO_SEL). See application section for part-to-part skew calculation. See application section for a jitter calculation for other confidence factors than 1 . -3 dB point of PLL transfer characteristics.
TIMING SOLUTIONS
7
MOTOROLA
MPC9774
APPLICATIONS INFORMATION
MPC9774 Configurations Configuring the MPC9774 amounts to properly configuring the internal dividers to produce the desired output frequencies. The output frequency can be represented by this formula:
fOUT = fREF M / N fREF PLL /VCO_SEL /N fOUT
the VCO_SEL pin. VCO_SEL effectively extends the usable input frequency range while it has no effect on the output to reference frequency ratio. The output frequency for each bank can be derived from the VCO frequency and the output divider: fQA[4:0] = fVCO / (VCO_SEL NA) fQB[4:0] = fVCO / (VCO_SEL NB) fQC[3:0] = fVCO / (VCO_SEL NC) Table 11. MPC9774 Divider
Divider Function PLL feedback FSEL_FB[0:2] Bank A Output Divider FSEL_A Bank B Output Divider FSEL_B Bank C Output Divider FSEL_C VCO_SEL /2 /4 /2 /4 /2 /4 /2 /4 Values 8, 12, 16, 24 16, 24, 32, 48 4, 8 8, 16 4, 8 8, 16 8, 12 16, 24 M NA NB NC
/M
where fREF is the reference frequency of the selected input clock source (CCLKO or CCLK1), M is the PLL feedback divider and N is a output divider. M is configured by the FSEL_FB[0:1] and N is individually configured for each output bank by the FSEL_A, FSEL_B and FSEL_C inputs. The reference frequency fREF and the selection of the feedback-divider M is limited by the specified VCO frequency range. fREF and M must be configured to match the VCO frequency range of 200 to 5001 MHz (VCC = 3.3V) in order to achieve stable PLL operation: fVCO,MIN
(fREF VCO_SEL M) fVCO,MAX
The PLL post-divider VCO_SEL is either a divide-by-two or a divide-by-four and can be used to situate the VCO into the specified frequency range. This divider is controlled by
1. The VCO frequency range for 2.5V operation is specified from 200 to 400 MHz. Table 11 shows the various PLL feedback and output dividers. The output dividers for the three output banks allow the user to configure the outputs into 1:1, 2:1, 3:2 and 3:2:1 frequency ratios. Figure 3 and Figure 4 display example configurations for the MPC9774:
Figure 3. Example Configuration
fref = 20.83 MHz 0 0 0 1 0 10 CCLK0 CCLK1 CCLK_SEL VCO_SEL FB_IN QA[4:0] QB[4:0] 125 MHz 62.5 MHz
Figure 4. Example Configuration
fref = 25 MHz 0 0 0 1 1 01 CCLK0 CCLK1 CCLK_SEL VCO_SEL FB_IN QA[4:0] QB[4:0] 100 MHz 50 MHz
FSEL_A QC[3:0] FSEL_B FSEL_C QFB FSEL_FB[1:0]
MPC9774
62.5 MHz
FSEL_A QC[3:0] FSEL_B FSEL_C QFB FSEL_FB[1:0]
MPC9774
33.3 MHz
20.83 MHz (Feedback)
25 MHz (Feedback)
MPC9774 example configuration (feedback of QFB = 20.83 MHz, VCO_SEL = /2, M = 12, NA = 2, NB = 4, NC = 4, fVCO = 500 MHz).
Frequency range Input QA outputs QB outputs QC outputs Min 8.33 MHz 50 MHz 25 MHz 25 MHz Max 20.83 MHz 125 MHz 62.5 MHz 62.5 MHz
MPC9774 example configuration (feedback of QFB = 25 MHz, VCO_SEL = /2, M = 8, NA = 2, NB = 4, NC = 6, fVCO = 400 MHz).
Frequency range Input QA outputs QB outputs QC outputs Min 20 MHz 50 MHz 50 MHz 100 MHz Max 48 MHz 120 MHz 120 MHz 200 MHz
MOTOROLA
8
TIMING SOLUTIONS
MPC9774
Using the MPC9774 in zero-delay applications Nested clock trees are typical applications for the MPC9774. Designs using the MPC9774 as LVCMOS PLL fanout buffer with zero insertion delay will show significantly lower clock skew than clock distributions developed from CMOS fanout buffers. The external feedback of the MPC9774 clock driver allows for its use as a zero delay buffer. The PLL aligns the feedback clock output edge with the clock input reference edge resulting a near zero delay through the device (the propagation delay through the device is virtually eliminated). The maximum insertion delay of the device in zero-delay applications is measured between the reference clock input and any output. This effective delay consists of the static phase offset, I/O jitter (phase or long-term jitter), feedback path delay and the output-to-output skew error relative to the feedback output. Table 12. MPC9774 Divider
CF 1s 2s 3s 4s 5s 6s Probability of clock edge within the distribution 0.68268948 0.95449988 0.99730007 0.99993663 0.99999943 0.99999999
The feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. In the following example calculation a I/O jitter confidence factor of 99.7% ( 3) is assumed, resulting in a worst case timing uncertainty from input to any output of -495 ps to 495 ps2 relative to CCLK:
Calculation of part-to-part skew The MPC9774 zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs of two or more MPC9774 are connected together, the maximum overall timing uncertainty from the common CCLK input to any output is:
tSK(PP) = tSK(PP) =
[-300ps...300ps] + [-150ps...150ps] + [(15ps @ -3)...(15ps @ 3)] + tPD, LINE(FB) [-495ps...495ps] + tPD, LINE(FB)
Due to the frequency dependence of the I/O jitter, Figure 6 can be used for a more precise timing performance analysis. TBD. See MPC961C application section for an example I/O jitter characteristic
tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT()
CF
This maximum timing uncertainty consist of 4 components: static phase offset, output skew, feedback board trace delay and I/O (phase) jitter: Figure 6. 2. Final skew data pending specification
CCLKCommon
Driving Transmission Lines
-t() tPD,LINE(FB)
QFBDevice 1
tJIT() tSK(O) +t()
Any QDevice 1
QFBDevice2
tJIT() tSK(O) tSK(PP)
Any QDevice 2 Max. skew
The MPC9774 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to Motorola application note AN1091. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC / 2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9774 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 7 "Single versus Dual Transmission Lines" illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the MPC9774 clock driver is effectively doubled due to its capability to drive multiple lines.
Figure 5. MPC9774 max. device-to-device skew
Due to the statistical nature of I/O jitter a rms value (1 ) is specified. I/O jitter numbers for other confidence factors (CF) can be derived from Table 12.
TIMING SOLUTIONS
9
MOTOROLA
MPC9774
towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0ns).
MPC9774 OUTPUT BUFFER IN
14
3.0 ZO = 50 OutA VOLTAGE (V) 2.0 In 1.5 OutA tD = 3.8956 OutB tD = 3.9386
RS = 36
2.5
MPC9774 OUTPUT BUFFER IN
14
RS = 36
ZO = 50 OutB0
1.0 RS = 36 ZO = 50 OutB1 0.5
0
Figure 7. Single versus Dual Transmission Lines The waveform plots in Figure 8 "Single versus Dual Line Termination Waveforms" show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9774 output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9774. The output waveform in Figure 8 "Single versus Dual Line Termination Waveforms" shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36 series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: = VS ( Z0 / (RS + R0 + Z0)) = 50 || 50 = 36 || 36 = 14 = 3.0 ( 25 / (18 + 17 + 25) = 1.31V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.6V. It will then increment VL Z0 RS R0 VL
2
4
6
8 TIME (nS)
10
12
14
Figure 8. Single versus Dual Waveforms Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 9 "Optimized Dual Line Termination" should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched.
MPC9774 OUTPUT BUFFER
14
RS = 22
ZO = 50
RS = 22
ZO = 50
14 + 22 k 22 = 50 k 50 25 = 25 Figure 9. Optimized Dual Line Termination
MOTOROLA
10
TIMING SOLUTIONS
MPC9774
Power Supply Filtering The MPC9774 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCC_PLL power supply impacts the device characteristics, for instance I/O jitter. The MPC9774 provides separate power supplies for the output buffers (VCC) and the phase-locked loop (VCC_PLL) of the device.The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simple but effective form of isolation is a power supply filter on the VCC_PLL pin for the MPC9774. Figure 10 illustrates a typical power supply filter scheme. The MPC9774 frequency and phase stability is most susceptible to noise with spectral content in the 100 kHz to 20 MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor RF. From the data sheet the ICC_PLL current (the current sourced through the VCC_PLL pin) is typically 3 mA (5 mA maximum), assuming that a minimum of 2.325V (VCC = 3.3V or VCC = 2.5V) must be maintained on the VCC_PLL pin. The resistor RF shown in MPC9774 must have a resistance of 9-10 (VCC = 2.5V) to meet the voltage drop criteria. The minimum values for RF and the filter capacitor CF are defined by the required filter characteristics: the RC filter should provide an attenuation greater than 40 dB for noise whose spectral content is above 100 kHz. In the example RC filter shown in MPC9774, the filter cut-off frequency is around 3-5 kHz and the noise attenuation at 100 kHz is better than 42 dB.
RF = 9-10 RF VCC CF 10 nF CF = 22 F VCC_PLL MPC9774 VCC 33...100 nF
Figure 10. VCC Power Supply Filter As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the MPC9774 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs.
MPC9774 DUT Pulse Generator Z = 50W Z = 50 Z = 50
RT = 50 VTT
RT = 50 VTT
Figure 11. CCLK MPC9774 AC test reference for Vcc = 3.3V and Vcc = 2.5V
TIMING SOLUTIONS
11
MOTOROLA
MPC9774
VCC VCC VCC VCC
B2
CCLKx
GND
B2
FB_IN
VCC VCC VCC VCC
B2 B2
GND
GND tSK(O) The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device
GND t()
Figure 12. Output-to-output Skew tSK(O)
VCC VCC tP T0 DC = tP /T0 x 100% The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage
Figure 13. Propagation delay (t(), static phase offset) test reference
CCLKx
B2
GND FB_IN
TJIT() = |T0 -T1 mean| The deviation in t0 for a controlled edge with respect to a t0 mean in a random sample of cycles
Figure 14. Output Duty Cycle (DC)
Figure 15. I/O Jitter
TN
TN+1
tJIT(CC) = |TN - TN + 1 |
T0
tJIT(PER) = |TN - (1 / f0 )|
The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs
The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles
Figure 16. Cycle-to-cycle Jitter
Figure 17. Period Jitter
VCC = 3.3V 2.4 0.55 tF tR
VCC = 2.5V 1.8V 0.6V
Figure 18. Output Transition Time Test Reference
MOTOROLA
12
TIMING SOLUTIONS
MPC9774
OUTLINE DIMENSIONS
FA SUFFIX 52 LEAD LQFP PACKAGE CASE 848D-03 ISSUE D
4X 4X 13 TIPS
0.20 (0.008) H L-M N
0.20 (0.008) T L-M N
52 1
40 39
-X- X=L, M, N C L -M- B V AB B1 VIEW Y V1
NOTES: 1 DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION: MILLIMETER. 3 DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4 DATUMS -L-, -M- AND -N- TO BE DETERMINED AT DATUM PLANE -H-. 5 DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -T-. 6 DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7 DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46 (0.018). MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0.07 (0.003). MILLIMETERS MIN MAX 10.00 BSC 5.00 BSC 10.00 BSC 5.00 BSC --- 1.70 0.05 0.20 1.30 1.50 0.20 0.40 0.45 0.75 0.22 0.35 0.65 BSC 0.07 0.20 0.50 REF 0.08 0.20 12.00 BSC 6.00 BSC 0.09 0.16 12.00 BSC 6.00 BSC 0.20 REF 1.00 REF 0_ 7_ --- 0_ 12 _ REF 12 _ REF INCHES MIN MAX 0.394 BSC 0.197 BSC 0.394 BSC 0.197 BSC --- 0.067 0.002 0.008 0.051 0.059 0.008 0.016 0.018 0.030 0.009 0.014 0.026 BSC 0.003 0.008 0.020 REF 0.003 0.008 0.472 BSC 0.236 BSC 0.004 0.006 0.472 BSC 0.236 BSC 0.008 REF 0.039 REF 0_ 7_ --- 0_ 12 _ REF 12 _ REF
3X
VIEW Y
-L-
AB
G
13 14 26
27
A1 S1 A S
-N-
C -H- -T-
SEATING PLANE
4X
q2
0.10 (0.004) T
4X
q3
VIEW AA
0.05 (0.002)
S
W
q1
C2
2X R
R1
0.25 (0.010)
q
GAGE PLANE
K C1 E VIEW AA Z J
PLATING
F
BASE METAL
U
DIM A A1 B B1 C C1 C2 D E F G J K R1 S S1 U V V1 W Z 1 2 3
0.13 (0.005)
SECTION AB-AB
ROTATED 90_ CLOCKWISE
TIMING SOLUTIONS
CCCC EEEE CCCC EEEE
M
D T L-M
S
N
S
13
MOTOROLA
MPC9774
NOTES
MOTOROLA
14
TIMING SOLUTIONS
MPC9774
NOTES
TIMING SOLUTIONS
15
MOTOROLA
MPC9774
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. MOTOROLA and the logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners.
E Motorola, Inc. 2002.
How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu. Minato-ku, Tokyo 106-8573 Japan. 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852-26668334 Technical Information Center: 1-800-521-6274 HOME PAGE: http://www.motorola.com/semiconductors/
MOTOROLA
16
MPC9774/D TIMING SOLUTIONS

▲Up To Search▲

Price & Availability of MPC9774

	To Download MPC9774 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .